                1. Background of the Invention        
The present invention relates to test mode circuits of semiconductor memory devices, and more specifically, to a test mode circuit of a semiconductor memory device which reduces the number of metal lines used for selecting a test mode item by grouping the test mode items.
2. Description of the Prior Art
FIG. 1 is a block diagram illustrating a conventional test mode circuit of a semiconductor memory device.
The conventional test mode circuit comprises a test mode controller 1, an address decoder 2 and a test mode decoder 3.
The test mode controller 1 is controlled by a mode register set signal MRS, and outputs a test mode setting signal TMS and a test mode end signal TME for setting a test mode depending on states of an address signal ADD<7>.
The mode register set signal MRS is generated at a rising edge of an inputted clock signal when a row address strobe signal /RAS, a column address strobe signal /CAS, a chip selecting signal /CS and a write enable signal /WE are simultaneously at a low level (not shown).
The address decoder 2 decodes address signals ADD<0:5>, and outputs decoding address signals TMADD<0:63> for selecting each test mode item. Here, a test mode circuit using 64 test mode items is exemplified. Accordingly, the decoding address signal TMADD<0:63> of 64 bits obtained by decoding the address signal ADD<0:5> of 6 bits is used to select each test mode item.
The test mode decoder 3 is controlled by the test mode setting signal TMS and the test mode end signal TME, and selects each test mode item in response to the decoding address signals TMADD<0:63>. The test mode decoder 3 activates corresponding test mode item selecting signals TM<0:63> to select a specific test mode item so that a test may be performed using the specific test mode item.
FIG. 2 is a circuit diagram illustrating the test mode controller 1 of FIG. 1.
The test mode controller 1 comprises NAND gates NDS and NDE, and inverters INS and INE. The NAND gate NDS performs a NAND operation on the mode register set signal MRS and the address signal ADD<7>. The inverter INS inverts an output signal from the NAND gate NDS, and outputs the test mode setting signal TMS. The NAND gate NDE performs a NAND operation on the mode register set signal MRS and an inverted address signal /ADD<7> outputted by the inverter INV. The inverter INE inverts an output signal from the NAND gate NDE, and outputs the test mode end signal TME.
FIG. 3 is a circuit diagram illustrating the address decoder 2 of FIG. 1.
The address decoder 2 comprises inverters INV0˜INV5, NAND gates ND10˜ND163, and inverters INV10˜INV163. The inverters INV0˜INV5 invert address signals ADD<0:5>, respectively. The NAND gates ND10˜ND163 perform NAND operations on address signals ADD<0:5> and output signals from the inverters INV0˜INV5. The inverters INV10˜INV163 invert output signals from the NAND gates ND10˜ND163, and output decoding address signals TMADD<0:63>.
FIG. 4 is a circuit diagram illustrating the test mode decoder 3 of FIG. 1.
The test mode decoder 3 comprises 64 test mode item selecting means 4. The test mode item selecting means 4 is controlled by the test mode setting signal TMS and the test mode end signal TME, and outputs test mode item selecting signals TM<0:63> for selecting each test mode item in response to the decoding address signals TMADD<0:63>.
Each test mode item selecting means 4 comprises a PMOS transistor PM1, NMOS transistor NM1 and NM2, and a latch 5. The PMOS transistor PM1 has a gate to receive the test mode end signal TME. The NMOS transistor NM1 has a gate to receive the test mode setting signal TMS. The NMOS transistor NM2 has a gate to receive a corresponding signal of the decoding address signals TMADD<0:63>. The latch 5 is connected to a common drain of the PMOS transistor PM1 and the NMOS transistor NM1. The latch 5 comprises inverters INL1 and INL2. An output signal from the inverter INL1 is inputted to an input terminal of the inverter INL2, and an output signal from the inverter INL2 is inputted to an input terminal of the inverter INL1.
Next, the operation of the conventional test mode circuit is described.
If a system is activated when the mode register set signal MRS transitions to a high level, a test mode is set depending on the state of the address signal ADD<7>.
If the address signal ADD<7> is at a high level, the test mode setting signal TMS transitions to a high level to activate the test mode.
When one of the decoding address signals TMADD<0:63> transitions to a high level, a test mode item selecting signal outputted from the corresponding test mode item selecting means 4 is enabled to a high level.
Thereafter, a test circuit corresponding to the activated test mode item selecting signal sets a test mode, and is prepared to perform a test.
In the conventional test mode circuit, the peripheral circuit region is enlarged because a corresponding metal line is required for setting each test mode item. As a result, cell efficiency is degraded.